SNVS698F April 2011 – August 2015 LM5117 , LM5117Q1
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM5117 is a stepdown dcdc controller. The device is typically used to convert a higher dcdc voltage to a lower dc voltage. Use the following design procedure to select component values. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an iterative design procedure and assesses a comprehensive database of components when generating a design.
Open loop response of the regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain.
The modulator transfer function includes a power stage transfer function with an embedded current loop and can be simplified as one pole and one zero system as shown in Equation 15.
If the ESR of C_{OUT} (R_{ESR}) is very small, the modulator transfer function can be further simplified to a one pole system and the voltage loop can be closed with only two loop compensation components, R_{COMP} and C_{COMP}, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.
The feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. R_{COMP}, C_{COMP} and optional C_{HF} configure the error amplifier gain and phase characteristics and create a pole at origin, a low frequency zero and a high frequency pole. This is shown mathematically in Equation 16.
The pole at the origin minimizes output steady state error. The low frequency zero should be placed to cancel the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. The high frequency pole should be placed well beyond the crossover frequency since the addition of C_{HF} adds a pole in the feedback transfer function.
The crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the f_{SW}. In a simplified formula, the crossover frequency can be defined as:
For higher crossover frequency, R_{COMP} can be increased, while proportionally decreasing C_{COMP}. Conversely, decreasing R_{COMP} while proportionally increasing C_{COMP}, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function.
The sampled gain inductor pole is inversely proportional to the K factor, which is defined as:
The maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. In traditional current mode control, the maximum achievable loop bandwidth varies with input voltage. With the LM5117’s unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input voltage. This frees the user from additional concerns in wide varying input range applications and is an advantage of the LM5117.
If the sampled gain inductor pole or the ESR zero is close to the crossover frequency, it is recommended that the comprehensive formulas in Table 1 be used and the stability should be checked by a network analyzer. The modulator transfer function can be measured and the feedback transfer function can be configured for the desired open loop transfer function. If a network analyzer is not available, step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a damped response.
Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as subharmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Subharmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation) on top of the sensed inductor current shown in Figure 20. By choosing K≥1, the regulator will not be subject to subharmonic oscillation caused by a varying input voltage.
In timedomain analysis, the steadystate inductor current starts and ends at the same value during one clock cycle. If the magnitude of the endofcycle current error, dI_{1}, caused by an initial perturbation, dI_{0}, is less than the magnitude of dI_{0} or dI_{1}/dI_{0} > 1, the perturbation naturally disappears after a few cycles. When dI_{1}/dI_{0} < 1, the initial perturbation does not disappear, resulting in subharmonic oscillation in steadystate operation.
dI_{1}/dI_{0} can be calculated by:
The relationship between dI_{1}/dI_{0} and K factor is illustrated graphically in Figure 31.
The minimum value of K is 0.5. When K<0.5, the amplitude of dI_{1} is greater than the amplitude of dI_{0} and any initial perturbation results in subharmonic oscillation. If K=1, any initial perturbation will be removed in one switching cycle. This is known as onecycle damping. When 1<dl_{1}/dl_{0}<0, any initial perturbation will be underdamped. Any perturbation will be overdamped when 0<dl_{1}/dl_{0}<1.
In the frequencydomain, Q, the quality factor of the sampling gain term in the modulator transfer function, is used to predict the tendency for subharmonic oscillation, which is defined as:
The relationship between Q and K factor is illustrated graphically in Figure 32.
The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator is unstable. High gain peaking at 0.5 results in subharmonic oscillation at F_{SW}/2. When K=1, onecycle damping is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency equation in Table 1.
DESIGN PARAMETER  EXAMPLE VALUE 

Output voltage  12 V 
Full load current, I_{OUT}  9 A 
Minimum input voltage, V_{IN(MIN)}  15 V 
Maximum input voltage, V_{IN(MAX)}  55 V 
Switching frequency, ƒ_{SW}  230 kHz 
Diode emulation  yes 
External VCC supply  yes 
Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected for this example as a reasonable compromise between small size and high efficiency. The value of R_{T} for 230 kHz switching frequency can be calculated from Equation 3 as follows:
A standard value of 22.1 kΩ was chosen for R_{T}.
The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load current is a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this example, a ripple current of 40% of 9 A was chosen. Knowing the switching frequency, maximum ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as follows:
The closest standard value of 10 μH was chosen for L_{O}. Using the value of 10 μH for L_{O}, calculate I_{PP} again. This step is necessary if the chosen value of L_{O} differs significantly from the calculated value.
From Equation 11,
At the minimum input voltage, this value is 1.04 A.
The DEMB pin is left floating since this example uses diode emulation to reduce the power loss under no load or light load conditions.
The performance of the converter will vary depending on the K value. For this example, K = 1 was chosen to control subharmonic oscillation and achieve onecycle damping. The maximum output current capability (I_{OUT(MAX)}) should be 20~50% higher than the required output current, to account for tolerances and ripple current. For this example, 130% of 9 A was chosen. The current sense resistor value can be calculated from Equation 9 and Equation 10 as follows:
A value of 7.41 mΩ was realized for R_{S} by placing an additional 0.1Ω sense resistor in parallel with 8 mΩ. The sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows through the lowside NMOS for the majority of the PWM cycle. The maximum power dissipation of R_{S} can be calculated as:
The worst case peak inductor current under the output short condition can be calculated from Equation 12 as follows:
where
The LM5117 itself is not affected by the large leading edge spike because it samples valley current just prior to the onset of the highside switch. A current sense filter is used to minimize a noise injection from any external noise sources. In general, a current sense filter is not necessary. In this example, a current sense filter is not used
Adding R_{CS} resistor changes the current sense amplifier gain which is defined as A_{S}=10 k / (1 k+R_{CS}). A small value of R_{CS} resistor below 100 Ω is recommended to minimize the gain change which is caused by the temperature coefficient difference between internal and external resistors.
The positive slope of the inductor current ramp signal is emulated by R_{RAMP} and C_{RAMP}. For this example, the value of C_{RAMP} was set at the standard capacitor value of 820 pF. With the inductor, sense resistor and the K factor selected, the value of R_{RAMP} can be calculated from Equation 4 as follows:
The standard value of 165 kΩ was selected for R_{RAMP}.
The desired startup voltage and the hysteresis are set by the voltage divider R_{UV1} and R_{UV2}. Capacitor C_{FT} provides filtering for the divider. For this design, the startup voltage was set to 14 V, 1 V below V_{IN(MIN)}. V_{HYS} was set to 2 V. The value of R_{UV1}, R_{UV2} can be calculated from Equation 1 and Equation 2 as follows:
The standard value of 100 kΩ was selected for R_{UV2}. R_{UV1} was selected to be 9.76 kΩ. A value of 47 pF was chosen for C_{FT}.
The 12V output voltage allows the external VCC supply configuration as shown in Figure 16. In this example, VCCDIS can be left floating since V_{OUT} is higher than VCC regulator setpoint level.
Selection of the power NMOS devices is governed by the same tradeoffs as switching frequency. Breaking down the losses in the highside and lowside NMOS devices is one way to compare the relative efficiencies of different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging loss, and switching loss.
Conduction loss P_{DC} is approximately:
where
Alternatively, the factor of 1.3 can be eliminated and the high temperature onresistance of the NMOS device can be estimated using the R_{DS(ON)} vs Temperature curves in the MOSFET datasheet.
Gate charging loss (P_{GC}) results from the current driving the gate capacitance of the power NMOS devices and is approximated as:
Qg refers to the total gate charge of an individual NMOS device, and ‘n’ is the number of NMOS devices. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC. Switching loss (P_{SW}) occurs during the brief transition period as the highside NMOS device turns on and off. During the transition period both current and voltage are present in the channel of the NMOS device. The switching loss can be approximated as:
t_{R} and t_{F} are the rise and fall times of the highside NMOS device. The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the highside NMOS device only. Switching loss in the lowside NMOS device is negligible because the body diode of the lowside NMOS device turns on before and after the lowside NMOS device switches. For this example, the maximum draintosource voltage applied to either NMOS device is 55 V. The selected NMOS devices must be able to withstand 55 V plus any ringing from drain to source and must be able to handle at least the VCC voltage plus any ringing from gate to source.
A resistorcapacitor snubber network across the lowside NMOS device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50 Ω. Increasing the value of the snubber capacitor results in more damping, but higher snubber losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. A snubber may not be necessary with an optimized layout.
The bootstrap capacitor between the HB and SW pin supplies the gate current to charge the highside NMOS device gate during each cycle’s turnon and also supplies recovery charge for the bootstrap diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1 μF. C_{HB} should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap capacitor is calculated as:
where
A value of 0.47 μF was selected for this design.
The primary purpose of the VCC capacitor (C_{VCC}) is to supply the peak transient currents of the LO driver and bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The recommended value of C_{VCC} should be no smaller than 0.47μF, and should be a good quality, low ESR, ceramic capacitor. C_{VCC} should be placed at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. A value of 1 μF was selected for this design.
The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of charge during transient loading conditions. For this design example, a 470μF electrolytic capacitor with maximum 20mΩ ESR was selected as the main output capacitor. The fundamental component of the output ripple voltage with maximum ESR is approximated as:
Additional low ERS / ESL ceramic capacitors can be placed in parallel with the main output capacitor to further reduce the output voltage ripple and spikes. In this example, two 22μF capacitors were added.
The regulator input supply voltage typically has high source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the ontime. When the highside NMOS device turns on, the current into the device steps to the valley of the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input capacitor should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is I_{RMS} > I_{OUT} / 2.
In this example, seven 3.3μF ceramic capacitors were used. With ceramic capacitors, the input ripple voltage will be triangular. The input ripple voltage can be approximated as:
Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the input capacitors based on the relative impedance of the capacitors at the switching frequency.
An RC filter (R_{VIN}, C_{VIN}) on VIN is optional. The filter helps to prevent faults caused by high frequency switching noise injection into the VIN pin. A 0.47μF ceramic capacitor is used for C_{VIN} in the example. R_{VIN} is selected to be 3.9 Ω.
The capacitor at the SS pin (C_{SS}) determines the softstart time (t_{SS}), which is the time for the output voltage to reach the final regulated value. The t_{SS} for a given C_{SS} can be calculated from Equation 8 as follows:
For this example, a value of 0.1 μF was chosen for a softstart time of 8 ms.
The capacitor at the RES pin (C_{RES}) determines t_{RES}, which is the time the LM5117 remains off before a restart attempt is made in hiccup mode current limiting. t_{RES} for a given C_{RES} can be calculated from Equation 13 as follows:
For this example, a value of 0.47 μF was chosen for a restart time of 59 ms.
R_{FB1} and R_{FB2} set the output voltage level. The ratio of these resistors is calculated as:
The ratio between R_{COMP} and R_{FB2} determines the midband gain, A_{FB_MID}. A larger value for R_{FB2} may require a corresponding larger value for R_{COMP}. R_{FB2} should be large enough to keep the total divider power dissipation small. 4.99 kΩ was chosen for R_{FB2} in this example, which results in a R_{FB1} value of 357 Ω for 12V output.
R_{COMP}, C_{COMP} and C_{HF} configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the 4 steps listed below.
STEP1: Select f_{CROSS}
By selecting one tenth of the switching frequency, f_{CROSS} is calculated as follows:
STEP2: Determine required R_{COMP}
Knowing f_{CROSS}, R_{COMP} is calculated as follows:
The standard value of 27.4kΩ was selected for R_{COMP}
STEP3: Determine C_{COMP} to cancel load pole
Knowing R_{COMP}, C_{COMP} is calculated as follows:
The standard value of 22nF was selected for C_{COMP}
STEP4: Determine C_{HF} to cancel ESR zero
Knowing R_{COMP} and C_{COMP}, C_{HF} is calculated as follows:
Half of the maximum ESR is assumed as a typical ESR. The standard value of 180pF was selected for C_{HF}.
SIMPLE FORMULA  COMPREHENSIVE FORMULA^{(1)}  

MODULATOR TRANSFER FUNCTION 


Modulator DC Gain 


ESR Zero 


ESR Pole  Not considered 

Dominant Load Pole 


Sampled Gain Inductor Pole  Not considered 

Quality Factor  Not considered 

Subharmonic Double Pole  Not considered 

K Factor 


FEEDBACK TRANSFER FUNCTION 


Feedback DC Gain 


Midband Gain 


Low Frequency Zero 


High Frequency Pole 


OPENLOOP RESPONSE 





Cross Over Frequency (Open Loop Bandwidth) 


Maximum Cross Over Frequency 

The frequency at which 45° phase shift occurs in modulator phase characteristics. 
The LM5117 can be configured as a constant current regulator by using the current monitor feature (CM) as the feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output overvoltage. When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the VCC regulator and the VCC pin voltage decays. When the VCC pin voltage is less than the VCC UV threshold, both HO and LO outputs stop switching. Due to the time delay required for VCC to decay below the VCC UV threshold, the overvoltage protection operates in hiccup mode. See Figure 35.
The LM5117 also can be configured as a constant voltage and constant current regulator, known as CV+CC regulator. In this configuration, there is much less variation in the current limiting as compared to peak cyclebycycle current limiting of the inductor current. The LMV431 and the PNP transistor create a voltagetocurrent amplifier in the current loop. This amplifier circuitry does not affect the normal operation when the output current is less than the current limit setpoint. When the output current is greater than the setpoint, the PNP transistor sources a current into C_{RAMP} and increases the positive slope of emulated inductor current ramp until the output current is less than or equal to the current limit setpoint. See Figure 36 and Figure 37.